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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog 6th Edition, ISBN-13: 978-0134549897

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Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog 6th Edition, ISBN-13: 978-0134549897

[PDF eBook eTextbook]

  • Publisher: ‎ Pearson; 6th edition (March 7, 2017)
  • Language: ‎ English
  • 720 pages
  • ISBN-10: ‎ 9780134549897
  • ISBN-13: ‎ 978-0134549897

The speed, density, and complexity of today’s digital devices are made possible by advances in physical processing technology and digital design methodology. Aside from semiconductor technology, the design of leading-edge devices depends critically on hardware description languages (HDLs) and synthesis tools. Three public-domain languages, Verilog, VHDL, and SystemVerilog, all play a role in design flows for today’s digital devices. HDLs, together with fundamental knowledge of digital logic circuits, provide an entry point to the world of digital design for students majoring in computer science, computer engineering, and electrical engineering.

In the not-too-distant past, it would be unthinkable for an electrical engineering student to graduate without having used an oscilloscope. Today, the needs of industry demand that undergraduate students become familiar with the use of at least one hardware description language. Their use of an HDL as a student will better prepare them to be productive members of a design team after they graduate.

Given the presence of three HDLs in the design arena, we have expanded our presentation of HDLs in Digital Design to treat Verilog and VHDL, and to provide an introduction to SystemVerilog. Our intent is not to require students to learn three, or even two, languages, but to provide the instructor with a choice between Verilog and VHDL while teaching a systematic methodology for design, regardless of the language, and an optional introduction to SystemVerilog. Certainly, Verilog and VHDL are widely used and taught, dominate the design space, and have common underlying concepts supporting combinational and sequential logic design, and both are essential to the synthesis of high-density integrated circuits. Our text offers parallel tracks of presentation of both languages, but allows concentration on a single language. The level of treatment of Verilog and VHDL is essentially equal, without emphasizing one language over the other. A language-neutral presentation of digital design is a – common thread through the treatment of both languages. A large set of problems, which are stated in language-neutral terms, at the end of each chapter can be worked with either Verilog or VHDL.

The emphasis in our presentation is on digital design, with HDLs in a supporting role. Consequently, we present only those details of Verilog, VHDL, and SystemVerilog that are needed to support our treatment of an introduction to digital design. Moreover, although we present examples using each language, we identify and segregate the treatment of topics and examples so that the instructor can choose a path of presentation for a single language—either Verilog or VHDL. Naturally, a path that emphasizes Verilog can conclude with SystemVerilog, but it can be skipped without compromising the objectives. The introduction to SystemVerilog is selective—we present only topics and examples that are extensions of Verilog, and well within the scope of an introductory treatment. To be clear, we are not advocating simultaneous presentation of the languages. The instructor can choose either Verilog/SystemVerilog or VHDL as the core language supporting an introductory course in digital design. Regardless of the language, our focus is on digital design.

The language-based examples throughout the book are not just about the details of an HDL. We emphasize and demonstrate the modeling and verification of digital circuits having specified behavior. Neither Verilog or VHDL are covered in their entirety. Some details of the languages will be left to the reader’s continuing education and use of web resources. Regardless of language, our examples introduce a design methodology based on the concept of computer-aided modeling of digital systems by means of a mainstream, IEEE-standardized, hardware description language.

This revision of Digital Design begins each chapter with a statement of its objectives. Problems at the end of each chapter are combined with inchapter examples, and with in-chapter Practice Exercises. Together, these encounters with the subject matter bring the student closer to achieving the stated objectives and becoming skilled in digital design. Answers are given to selected problems at the end of each chapter. A Solution Manual gives detailed solutions to all of the problems at the end of the chapters. The level of detail of the solutions is such that an instructor can use individual problems to support classroom instruction.

Table of Contents:

Preface

1 Digital Systems and Binary Numbers

1.1 Digital Systems

1.2 Binary Numbers

1.3 NumberBase Conversions

1.4 Octal and Hexadecimal Numbers

1.5 Complements of Numbers

1.6 Signed Binary Numbers

1.7 Binary Codes

1.8 Binary Storage and Registers

1.9 Binary Logic

2 Boolean Algebra and Logic Gates

2.1 Introduction

2.2 Basic Definitions

2.3 Axiomatic Definition of Boolean Algebra

2.4 Basic Theorems and Properties of Boolean Algebra

2.5 Boolean Functions

2.6 Canonical and Standard Forms

2.7 Other Logic Operations

2.8 Digital Logic Gates

2.9 Integrated Circuits

3 GateLevel Minimization

3.1 Introduction

3.2 The Map Method

3.3 FourVariable K-Map

3.4 ProductofSums Simplification

3.5 Don’tCare Conditions

3.6 NAND and NOR Implementation

3.7 Other TwoLevel Implementations

3.8 ExclusiveOR Function

3.9 Hardware Description Languages (HDLs)

4 Combinational Logic

4.1 Introduction

4.2 Combinational Circuits

4.3 Analysis of Combinational Circuits

4.4 Design Procedure

4.5 Binary Adder—Subtractor

4.6 Decimal Adder

4.7 Binary Multiplier

4.8 Magnitude Comparator

4.9 Decoders

4.10 Encoders

4.11 Multiplexers

4.12 HDL Models of Combinational Circuits

5 Synchronous Sequential Logic

5.1 Introduction

5.2 Sequential Circuits

5.3 Storage Elements: Latches

5.4 Storage Elements: FlipFlops

5.5 Analysis of Clocked Sequential Circuits

5.6 Synthesizable HDL Models of Sequential Circuits

5.7 State Reduction and Assignment

5.8 Design Procedure

6 Registers and Counters

6.1 Registers

6.2 Shift Registers

6.3 Ripple Counters

6.4 Synchronous Counters

6.5 Other Counters

6.6 HDL Models of Registers and Counters

7 Memory and Programmable Logic

7.1 Introduction

7.2 RandomAccess Memory

7.3 Memory Decoding

7.4 Error Detection and Correction

7.5 ReadOnly Memory

7.6 Programmable Logic Array

7.7 Programmable Array Logic

7.8 Sequential Programmable Devices

8 Design at the Register Transfer Level

8.1 Introduction

8.2 Register Transfer Level (RTL) Notation

8.3 RTL descriptions VERILOG (Edge- and Level-Sensitive Behaviors)

8.4 Algorithmic State Machines (ASMs)

8.5 Design Example (ASMD Chart)

8.6 HDL Description of Design Example

8.7 Sequential Binary Multiplier

8.8 Control Logic

8.9 HDL Description of Binary Multiplier

8.10 Design with Multiplexers

8.11 RaceFree Design (Software Race Conditions)

8.12 LatchFree Design (Why Waste Silicon?)

8.13 System Verilog–An Introduction

9 Laboratory Experiments with Standard ICs and FPGAs

9.1 Introduction to Experiments

9.2 Experiment 1: Binary and Decimal Numbers

9.3 Experiment 2: Digital Logic Gates

9.4 Experiment 3: Simplification of Boolean Functions

9.5 Experiment 4: Combinational Circuits

9.6 Experiment 5: Code Converters

9.7 Experiment 6: Design with Multiplexers

9.8 Experiment 7: Adders and Subtractors

9.9 Experiment 8: FlipFlops

9.10 Experiment 9: Sequential Circuits

9.11 Experiment 10: Counters

9.12 Experiment 11: Shift Registers

9.13 Experiment 12: Serial Addition

9.14 Experiment 13: Memory Unit

9.15 Experiment 14: Lamp Handball

9.16 Experiment 15: ClockPulse Generator

9.17 Experiment 16: Parallel Adder and Accumulator

9.18 Experiment 17: Binary Multiplier

9.19 HDL Simulation Experiments and Rapid Prototyping with FPGAs

10 Standard Graphic Symbols

10.1 RectangularShape Symbols

10.2 Qualifying Symbols

10.3 Dependency Notation

10.4 Symbols for Combinational Elements

10.5 Symbols for FlipFlops

10.6 Symbols for Registers

10.7 Symbols for Counters

10.8 Symbol for RAM

Appendix

Answers to Selected Problems

Index

M. Morris Mano is an Emeritus Professor of Computer Engineering at the California State University, Los Angeles. His notable works include the Mano Machine, i.e. a theoretical computer that contains a central processing unit, random access memory, and an input-output bus. M. Morris Mano has authored numerous books in the area of digital circuits that are known for teaching the basic concepts of digital logic circuits in a clear, accessible manner. His books for the introductory digital design course, Logic and Computer Design Fundamentals and Digital Design, continue to be two of the most widely used texts around the world.

Michael Ciletti is an Emeritus Professor of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. An early advocate of including HDL-based design methodology in the curriculum, he pioneered and developed the offering of several courses using Verilog, VHDL, FPGAs and standard cell based hardware implementations for design, testing, and synthesis of VLSI devices. His consulting work has ranged from processor design to providing expert witness testimony in cases involving HDLs. He has developed and presented courses for industry in The United States, Asia, and Europe. His widely-adopted textbooks have promoted the use of the now-standard Verilog HDL and encouraged adoption of HDL-based design practice in logic design and computer science curricula. Ciletti resides in Colorado Springs, CO, where he pursues a strong interest in landscape photography.

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